AI Multi-agent Chip Design Verification Workflow
Agent1: Architect/Manager Agent2: RTL Designer Agent3: Verification Engineer Agent4: Synthesis Engineer Agent5: Timing and Implementer
AI based UVM Testbench Generator
Input: RTL design LLM Model: Free Ollama and paid ones with API keys output: Testbench and running scripts
AI based Cocotb Testbench Generator
Input: RTL design LLM Model: Free Ollama and paid ones with API keys output: Testbench and running scripts