Hierarchical MARL/LLM QSIM EDA flow For PPA/Sign-off
From RTL-to-GDSII (For TNS/WTNS/DRC/Power/Area synergy optimization and speedup sign-off)
AI Co-design RISC-V SOC IDE
Using an autonomous AI agent to automate the painfully slow and expensive process of hardware/software co-design, turning months of manual engineering into hours of automated execution.
AI Multi-agent Chip Design Verification Workflow
Agent1: Architect/Manager Agent2: RTL Designer Agent3: Verification Engineer Agent4: Synthesis Engineer Agent5: Timing and Implementer
AI based UVM Testbench Generator
Input: RTL design LLM Model: Free Ollama and paid ones with API keys output: Testbench and running scripts
AI based Cocotb Testbench Generator
Input: RTL design LLM Model: Free Ollama and paid ones with API keys output: Testbench and running scripts
SoC Design Verification AI Assistant
Assembly, C and RTL programs generator & simulator
Mixed Signals Design Verification AI Assistant
SPICE and RTL programs generator & simulator with ADC/DAC